1. Field of the Invention
The present invention relates to write and read operations and a memory structure of a semiconductor memory device.
2. Description of the Related Art
Recently, as small-size and high-performance electronic apparatuses having a memory function, such as a portable terminal apparatus, an IC card, and the like, have become widespread, there is an increasing demand for a low-voltage, low-power consumption, and high-speed operation semiconductor memory device suitable for these apparatuses. Particularly, there is a high demand for nonvolatile memories, such as, representatively, a flash memory. In terms of low power consumption and high speed operation, a ferroelectric memory has attracted attention. The ferroelectric memory is structured to utilize a difference between the polarization directions of a capacitor made of a ferroelectric film and thereby to store nonvolatile data. Therefore, data can be rewritten only by applying an electric field for reversing the polarization direction, whereby the ferroelectric memory is characterized by a low voltage, low power consumption, and a high speed operation.
FIG. 1 is a circuit diagram of a conventional exemplary memory cell portion, and FIG. 2 is a conventional exemplary operation timing chart. See H. Hirano, et al., “High Density and Low Power Nonvolatile FeRAM with Non-Driven Plate and Selected Driven Bit-line Scheme”, 2004 Symposium on VLSI Circuits, Digest of Technical Papers, pp. 446-447, Jun. 2004.
FIG. 1 illustrates a portion of a two-transistor, two-capacitor (2T2C) memory cell array of a conventional ferroelectric memory, and peripheral circuitry thereof. BP indicates a bit line precharge signal, BP2 indicates a second bit line precharge signal, SAE indicates a sense amplifier start-up signal, WL0 to WL3 indicate first to fourth word lines, CP indicates a cell plate line, RST indicates a reset signal, BL0 and BL1 indicate first and second bit lines, 51 indicates a first memory cell transistor, 52 indicates a first ferroelectric capacitor, 53 indicates a first reset transistor, 54 indicates a second memory cell transistor, 55 indicates a second ferroelectric capacitor, and 56 indicates a second reset transistor. The second word line WL1 is connected to a gate of the first memory cell transistor 51, the first bit line BL0 is connected to a drain of the first memory cell transistor 51, and a first electrode of the first ferroelectric capacitor 52 is connected to a source (storage node) of the first memory cell transistor 51. The cell plate line CP is connected to a second electrode of the first ferroelectric capacitor 52. The reset signal RST is connected to a gate of the first reset transistor 53, the source of the first memory cell transistor 51 is connected to a drain of the first reset transistor 53, and the cell plate line CP is connected to a source of the first reset transistor 53. The second word line WL1 is connected to a gate of the second memory cell transistor 54, the second bit line BL1 is connected to a drain of the second memory cell transistor 54, and a first electrode of the second ferroelectric capacitor 55 is connected to a source (storage node) of the second memory cell transistor 54. The cell plate line CP is connected to a second electrode of the second ferroelectric capacitor 55. The reset signal RST is connected to a gate of the second reset transistor 56, the source of the second memory cell transistor 54 is connected to a drain of the second reset transistor 56, and the cell plate line CP is connected to a source of the second reset transistor 56. The first and second bit lines BL0 and BL1 are connected to the peripheral circuitry composed of a sense amplifier, a bit line precharge circuit, and the like. The cell plate line CP is fixed to 1/2VDD.
Next, a read operation and a rewrite operation when “H” data is held in the first ferroelectric capacitor 52 and “L” data is held in the second ferroelectric capacitor 55 in the above-described conventional example, will be described. Initially, it is assumed that, at time t01 of FIG. 2, BP and RST have a logic voltage “H”, and BP2, WL1, and SAE have a logic voltage “L”. In this case, the first and second bit lines BL0 and BL1, the cell plate line CP, and the sources of the first and second memory cell transistors 51 and 54 have a potential of 1/2VDD. Next, at time t02, when BP and RST are caused to go to the logic voltage “L”, the first and second bit lines BL0 and BL1 are turned into a floating state, so that the first and second reset transistors 53 and 56 are turned OFF. At time t03, when BP2 is caused to go to the logic voltage “H”, the first and second bit lines BL0 and BL1 are precharged to the logic voltage “L”. When BP2 is caused to go to the logic voltage “L” at time t04, and thereafter, WL1 is caused to go to a boosted potential VPP at time t05, the “H” data is read from the first ferroelectric capacitor 52, which holds the “H” data, and a potential corresponding to the “H” data appears on the first bit line BL0, and also, the “L” data is read from the second ferroelectric capacitor 55, which holds the “L” data, and a potential corresponding to the “L” data appears on the second bit line BL1. In this situation, at time t06, when SAE is caused to go to the logic voltage “H” to start up a sense amplifier, BL0 is amplified to the logic voltage “H” and BL1 is amplified to the logic voltage “L”. For time t09 to time t12, when the cell plate line CP has a potential of 1/2VDD, the logic voltage “H” is applied to the first bit line BL0, so that a potential of +1/2VDD is applied to the first ferroelectric capacitor 52, thereby the “H” data is rewritten into the first ferroelectric capacitor 52, and the logic voltage “L” is applied to the second bit line BL1, so that a potential of −1/2VDD is applied to the second ferroelectric capacitor 55, thereby the “L” data is rewritten into the second ferroelectric capacitor 55. Next, at time t12, when BP and RST are caused to go to the logic voltage “H” and SAE is caused to go to the logic voltage “L”, the first and second bit lines BL0 and BL1 go to 1/2VDD. Finally, at time t13, the read and rewrite operations are ended, where WL1 has the logic voltage “L”.
In the above-described conventional ferroelectric memory, when the memory is powered ON, the cell plate line CP is caused to go to 1/2VDD, and therefore, the second electrodes of the ferroelectric capacitors 52 and 55 connected to the cell plate line CP go to 1/2VDD. In this case, a potential difference occurs between the second electrodes and the floating-state first electrodes of the ferroelectric capacitors 52 and 55, so that the held data is destroyed. To prevent this, the reset transistors 53 and 56 are required as illustrated in FIG. 1, disadvantageously leading to an increase in chip size.